Breaking the "Pain of Materials": How Hanhua Semiconductor's 8-inch platform opens up the "Ren and Du" of compound semiconductors

In the wave of the post-Moore era, we have discussed in detail the charm of Micro-LED as the ultimate display technology. But behind that bright glimmer, there is an “invisible battlefield” that has long been ignored—heterogeneous integration.

In the past, the industry tended to focus on luminous efficiency or pixel size, but few people answered a soul question from the underlying logic of the semiconductor process: Why is gallium nitride (GaN), which has shown irreplaceable material advantages in core indicators such as photoelectric conversion efficiency and response speed, yet it is so limited? Trapped in process bottlenecks such as wafer size, defect density, and CMOS back-end heterogeneous integration, it has been unable to establish a mature and scalable manufacturing ecosystem like silicon-based semiconductors, making it difficult to unleash its full potential in AR micro-displays, optical interconnects, and other tracks that require high-density integration and low-cost mass production?

The key to the answer lies in "size". When compound semiconductor wafers stay at 4 inches or 6 inches for a long time, they are destined to be unable to access the 8-inch or even 12-inch equipment chains, material systems and process standards that the silicon-based IC industry has accumulated over decades, and can only struggle in the high-cost quagmire of "customized production lines." The 8-inch Micro-LED standard process platform recently built by Hanhua Semiconductor is of far more significance than the commissioning of a production line - it is essentially breaking the "size ceiling" and allowing compound semiconductors to merge from "material islands" into the mainstream IC manufacturing, paving the way for the next generation of space computing and optical interconnection era.

1. Incompatible "two mountains": the paradox of performance and manufacturing

To understand the significance of the Hanhua platform, we must first clarify the manufacturing gap between compound semiconductors and silicon-based ICs. From the perspective of physical attributes, these are two "languages": silicon-based IC is good at logical operations, but is inherently limited in photoelectric conversion; gallium nitride is the king of optoelectronic devices, but lacks a mature digital driver ecosystem. The ideal optical engine requires the cooperation of the two, but their manufacturing systems have fundamental conflicts:

· Physical integration challenges: Gallium nitride usually needs to be epitaxially grown on a heterogeneous substrate (such as sapphire or silicon). When directly integrated with silicon CMOS circuits, the huge differences in lattice constants and thermal expansion coefficients will cause the wafer to warp and crack.

· Production line compatibility barriers: Traditional compound semiconductor processes have large line widths and involve heavy metals and other pollutants, which are incompatible with silicon-based CMOS production lines that pursue ultimate purity and nanometer line widths. The two cannot coexist on the same standardized assembly line, and can only be "manufactured separately and spliced ​​later" - that is, manual assembly relies on techniques such as mass transfer, with extremely low yield and extremely high cost.

This deadlock of "compounds cannot be driven and integrated circuits cannot emit light" was finally broken by heterogeneous integration.

2. The "8-inch" line of life and death: the leap from "toy" to "tool"

In the integrated circuit industry, wafer size determines the ecological radius. The global silicon-based IC industry has developed for decades, and 8-inch (200mm) and 12-inch production lines have formed a mature equipment chain, material supply system and process standards. If compound semiconductors stay at 4 inches or 6 inches for a long time, it means low chip output per wafer, high degree of customization of 4/6-inch equipment, inability to enjoy the scale dividend of the IC industry, and high costs. Why is "8 inches" so critical? The reason is the scale effect of integrated circuits.

The core of Hanhua's breakthrough lies in the realization of 8-inch gallium nitride on silicon (GaN-on-Si) epitaxy and its lossless silicon removal technology. This includes two key leaps:

◆ Epitaxial layer breakthrough: growing a high-quality GaN epitaxial layer on an 8-inch silicon substrate. Through unique buffer layer technology, the cracking problem caused by lattice mismatch is solved, allowing the compound functional layer to meet the physical specifications of mainstream IC wafers.

◆ Breakthrough in stripping technology: "Destructive silicon removal" technology can completely strip off extremely thin GaN films, allowing them to enter standard production lines as "functional wafers".

This means that compound functional wafers can be "fed" directly into the 8-inch CMOS production line, and existing bonding, photolithography, etching and other equipment can be used to complete the back-end processes. This "size equivalence" is not a simple area expansion, but a qualitative change in the manufacturing paradigm - from "manual workshops" relying on special equipment to "standardized assembly lines" that share the ecosystem with silicon-based ICs.

3. Reconstructing the industrial ecology: Opto-mechanical engine and CPO's "Chinese base"

The reason why Hanhua's platform is of great significance is that it is not a closed factory, but an open optoelectronic integration standard process platform. It provides a deterministic localization path for the following frontier fields:

1. Spatial computing and near-eye display (AR/VR)

This is the most direct application scenario. One of the biggest challenges faced by devices such as the Apple Vision Pro is how to perfectly fit the bright Micro-LED pixel array with the silicon-based backplane driver circuit. Hanhua's "lossless silicon removal" technology allows us to peel off extremely thin gallium nitride films and combine them with 8-inch CMOS wafers through hybrid bonding technology. This kind of 3D heterogeneous integration not only solves the display problem, but also solves the heat dissipation and volume pain points. It is the key process foundation for realizing the "ordinary glasses size" spatial computing terminal.

2. Co-packaged optics (CPO): the “speed of light” in the era of computing power

In the era of large AI models, the data throughput between GPU clusters has approached the physical limit of copper wire interconnection, and CPO (co-packaging of optical engines and computing chips) has become a breakthrough direction. The core challenge of CPO is not "whether there are optoelectronic devices", but "whether optoelectronic devices can be manufactured with the precision and cost of chip manufacturing." Hanhua's 8-inch platform provides GaN optoelectronic functional layers of the same size as silicon-based ICs, allowing them to be directly stacked or integrated side by side next to silicon-based logic chips through the 3DIC process. This "chip" level optical and electrical integration is the physical basis for achieving bandwidths above 1.6Tbps and low-power optical interconnection.

3. Unified PDK logic: from "process black box" to standardized process interface

The most important contribution of the Hanhua platform is that it provides a standardized interface similar to the semiconductor process design kit (PDK). This solves the pain points of design companies: in the past, designing light engines required deep involvement in complex material process details; while the Hanhua platform standardizes and parameterizes processes such as GaN epitaxy, stripping, and bonding, and outputs a PDK interface similar to IC design. Design companies can design optoelectronic systems just like calling standard cell libraries, significantly lowering the technical threshold for heterogeneous integration - this is a key leap from "customized technology" to "platform ecology".

4. Conclusion: From augmented and reality display to computing, the full stack covers the future

The real significance of Hanhua Semiconductor's 8-inch heterogeneous three-dimensional integration platform is to break the "dimensional wall" between compound semiconductors and silicon-based integrated circuits. It solves the "large size" manufacturing problem, allowing compound semiconductors to no longer exist in isolation in special process production lines, but to incorporate them into the size standards, equipment ecology and process language shared with silicon-based ICs, embracing the "automated factory" era of the IC industry. On the platform it built, light is no longer a special existence independent of electricity, but has become a standard signal inside the chip.

When Micro-LED is no longer created for screens, but for transmitting data between chips; when we can use the large-scale equipment and processes used to manufacture CPUs to manufacture optical engines integrating 10,000-level light-emitting units - the beginning of spatial computing and photon computing will truly begin. This is the industrial significance of Hanhua Semiconductor's 8-inch platform: it is not catching up with the international level in terms of single device performance, but opening up a new track for compound semiconductors to merge with the silicon-based ecology in terms of manufacturing paradigm. When this track intersects with the industrial needs of space computing and photonic computing, it will truly have the key confidence to move from "single device catching up" to "system integration leadership".

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