TSMC announces CPO packaging and other technology layout

With the rapid growth of AI server computing requirements, data transmission delay and power consumption have become key bottlenecks that the industry urgently needs to overcome. In order to break through the physical limits of traditional copper wires, Compact Universal Photon Engine (COUPE) and co-optional optoelectronic packaging (CPO) technology are becoming the core solutions for the new generation of AI infrastructure, and have also become the focus of the semiconductor industry. It is expected that by significantly shortening the distance between optical components and core logic chips, future server transmission will usher in an astonishing leap in latency reduction by up to 95%.

Looking forward to breaking through the limits of copper wires and allowing optical transmission to penetrate deep into the core of servers, TSMC also made relevant explanations at the annual technology forum regarding Compact Universal Photon Engine (COUPE) and Optoelectronic Co-Packaging (CPO) technologies.

TSMC stated that in a typical AI server architecture, the connection between the GPU in the computing tray and the switch (Switch) responsible for data distribution has traditionally relied on copper wire connections, while optical transmission has been widely used between switches. In order to further improve the overall transmission performance, the industry is actively promoting compact optical packaging (COP). Its core concept is to "replace copper wires with optical transmission as much as possible", and even the last few centimeters on the circuit board are also converted to optical connections.

Yuan Liben, deputy general manager of TSMC's business development organization, pointed out that the core of this technology is to use SOIC (system integrated chip) technology to closely integrate ordinary logic chips (i.e. electronic integrated circuits, EICs) and optical chips (PICs). When the optical signal enters, the two chips will cooperate with each other to translate the optical signal into electrical signals and then output them to the core GPU.

Image source: TSMC

Packaging Technology Trilogy: The Ultimate Leap from Plug-in to Intermediate Layer

The evolution of silicon photonics packaging technology can be divided into three important stages:

Plug-in and circuit board level (On-PCB): This is the mainstream and existing solution in 2025. After photoelectric conversion, it is still necessary to run copper wires through long circuit boards and chip substrates. Although there has been progress, the transmission distance is still relatively long.

Substrate level (On-Substrate): A major development in the second half of 2026 is to move optical conversion components from the circuit board to the substrate of the chip package. Just shortening this tiny physical distance brings a significant performance jump. Data shows that CPO equipped with COUPE technology on the substrate can provide 4 times the power consumption efficiency of traditional copper wires and significantly reduce transmission delays by up to 90%.

On-Interposer: This is the next step in technology development and the key to advanced performance. By using COUPE technology on the middle layer to push optical components closer to the core computing unit, it is expected to achieve 10 times power efficiency and up to 95% latency reduction. Experts explain that the next stage of transmission rate improvement does not come from changes in optical speed itself, but because the physical transmission distance after the electrical signal is converted is closer to the logic computing core.

According to TSMC’s latest research and development progress, the world’s first 200Gbps microring modulator (MRM) equipped with COUPE technology is expected to enter mass production in 2026. Under excellent process control, MRM using this technology can achieve an extremely low error rate lower than 1E-08. Looking to the future, the industry will continue to expand technology capabilities and develop towards 400Gbps modulators, multi-wavelength technology and multi-column fiber array units. The ultimate goal is to achieve a bandwidth density of up to 4Tbps/mm in 2030.

Although the current CPO technology is still mainly used for data communication on the switch, the ultimate dream of industry experts including Quanta is to allow optical signals to directly cross the switch and enter the GPU. As advanced packaging technologies such as 3D Fabric continue to advance, in the future we are expected to see high-bandwidth memory (HBM), logic chips and optical packaging perfectly stacked in the same architecture, laying an unparalleled hardware foundation for the next generation of AI computing. (Source: Technews)

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